DailyJobs

Thursday, February 21, 2008

HOT JOBS in TI

HOT JOBS

Please click on the links below to read detailed job descriptions

 ASIC
 AEC
 DSPS
 SW
 HPA
 ITS
 Sales & Marketing

ASIC HOT JOBS

Position name – Memory Design Engineer / Lead
Experience: 3-5 years
Qualification: BE in Electronics

Additional Preferred Qualifications:
 Masters in any related VLSI, semiconductors subject.
 Experience or work on statistical methods or approaches of solving circuit design problems or work on variability in semiconductor processes and its effects is a wish list

Primary and Secondary Responsibilities:
 Will be responsible for memory compiler development for TI products. This will include core circuit design skills for actual memory design and development. Associated skills of scripting for task automation, characterization of the compilers is welcome. Any experience in memory design including tasks all the way from design, to actual characterization and silicon validation is what we are looking for.Type of memories may include ROM, embedded SRAM, CAM etc.
Complex Tasks:
 Complex tasks include actual circuit design of the memories in leading edge technology nodes like 65nm, 45nm and 32nm. This will include a solid understanding of the silicon development process and the variability effects of the same which need to be accounted for in designing of the memories. It will involve critical digital circuit design capabilities.
 The task will also encompass a complete compiler design in addition to the basic circuit design of the SRAM. This will include automation and scripting capabilities for characterization of the compilers as well as layout generation of the entire compiler through automated scripts.
 The compiler design will also include a very good understanding of the physical design and layouts of the memories and associated complexities of layout parasitics and effects on the design.
 A depth of understanding of the usage of memories in actual design context is also required to make the best tradeoffs and judgements on the compiler design.

Unique selling features of this position
 This is the only team working on memory solutions for the whole of TI and will be working on absolutely bleeding edge technology (45nm, 32nm) which involves working on circuit problems that are absolutely new in the whole industry. The company wide impact is also huge since this is a foundational IP and each and every single product in TI will be using these memories. There is a huge scope for innovation given the complexity of the problems being solved and based on interest , a very good chance for going on to the technical ladder.

AEC HOT JOBS


Position name – DFT Engineer

Experience: 3 to 5 years
Qualification: BE in Electronics

Additional Preferred Qualifications:
 Prior experience in DFT implementation, validation and post silicon support/debug
 Experience in Perl/Tcl scripting, DFT tools (memory bist, atpg), simulation tools (VCS, MODELSIM).
 Knowledge/understanding in Synthesis, STA.

Primary and Secondary Responsibilities:
 Define and Implement DFT structures, validate, support post-silicon bring-up and release to production efforts
 Architect SOC DFT



Position name – Verification Engineer

Experience: 1 to 5 years
Qualification: Bachelor’s engg degree in EE, ECE or Instrumentation

Additional Preferred Qualifications:

 VLSI awareness training
 Microcontroller assembly language programming

Primary and Secondary Responsibilities:
 Ownership of Digital Verification of various modules in a microcontroller and also many aspects of top (SoC) level features. The person should be able to handle assignments in verification domain within a month of being on-board after the project specific initiation. Expectation is that all assignments are completed on-time with focus on quality and completeness. Understanding of Standard cell and custom implementation, analysis of timing closure issues as seen in netlist regressions. The design is mixed-signal SoC which poses a lot of challenges.The person should be familiar with RTL design and synthesis flow. Is expected to participate and review designs and verification plans of others in the team.

Projects and Deliverables:
 Mixed-signal SoC designs
 Completion of module and SoC digital verification
 Mixed-signal modeling and verification completion
 Netlist regression completion and signoff
 Silicon test pattern generation and debug completion

Unique selling features of this position, team, or project:
Person will have the opportunity to design the next generation ultra low power microcontrollers and maintain TI's lead in this market

Position name – RTL/Circuit Design Engineer

Experience: 1 to 5 years
Qualification: Bachelor’s engg degree in EE, ECE or Instrumentation

Additional Preferred Qualifications:

 VLSI awareness training
 Microcontroller assembly language programming

Primary and Secondary Responsibilities:
 Primary responsibility for the person in this position is design of peripheral modules for TI's state of the art ultra low power microcontroller. Starting point will be top level specs or market needs. Detailed specifications have to be worked out and the module/peripheral design needs to be completed that is fully compliant with the specs. Ultra low power will be the primary design care about. The design could be a mixed signal one with fair amount of custom circuit design as well as synthesis based digital design. Design needs to be completed on time, along with all the supporting documentation.

 Person should be adept in taking up tasks in verification and validation domains depending on project needs. It is also expected to participate and review designs and verification plans completed by other engineers in the team.

 The person needs to be quite thorough in his/her understanding of electronics design concepts, VLSI design techniques and also in custom CMOS circuit design and basics of analog design. Need to be conversant in Verilog and/or VHDL languages, Cadence design environment for custom CMOS, SPICE and synthesis tools/constraints. Person is also expected to have a good understanding of timing and layout/physical design aspects associated with System-on-chip (SoC) designs.

 Tasks assigned are fairly complex since the expectation w.r.t. excellence to be achieved in the sphere of design and verification is fairly high.

 There is ample scope to come up with innovative designs to meet the stringent power requirements along with optimal area and performance goals. Opportunities also exist in creating modules that are bug-free or easy to ensure high verification and test coverage. Custom design style combined with digital design techniques poses its own challenges and hence opens up areas for innovation.

Projects and Deliverables:
 Mixed-signal SoC designs
 IP Block Design

Unique selling features of this position, team, or project:
Person will have the opportunity to design the next generation ultra low power microcontrollers and maintain TI's lead in this market.






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DSPS HOT JOBS


Position name – Sr Front End Design Engineer

Experience: 3 to 8 years
Qualification: Bachelor’s engg degree in Electronics and Communication Engineering

Primary Responsibilities

 Interaction with requirements-specification owners in defining and refining optimum feature-sets, subsequent micro-architecture definition for IPs and SOCs.
 Design and implementation of IP modules, related simulation, debug, synthesis and power/area/performance optimization.
 RTL implementation for SOC designs, related simulation, debug and RTL fixes.
 Synthesis/optimization and STA responsibilities for SOC designs.

Secondary Responsibilities

 QC of RTL using lint/DRC tools like Spyglass, equivalence checking using tools like LEC.
 Power/area analysis
 Gate-level simulation debug.
 RTL compile/flow setup/bring-up.
 Silicon bring-up/debug support is specific design areas as need arises.

Required Basic Qualification

 Well-versed with synthesizable behavioral logic implementation using Verilog.
-Experience with simulation and debug using ModelSim/VCS and Debussy.
 Sound knowledge and experience with Synopsys Design Compiler based synthesis of relatively large high-performance designs.
 Experience and strong knowledge on all aspects of Static Timing Analysis using Primetime.
Additional Preferred Qualifications:
 Experience with requirement specification and detailed architecture of relatively complex designs.
 Experience with chip-level RTL integration of relatively large SOCs.
 Experience with using Equivalence checker tools like LEC.
 Knowledge on Design For Test and Manufacturability (DFTM) aspects.
 Knowledge on design implementation using VHDL will be an advantage.
 Experience with verification and test-bench development.











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SOFTWARE HOT JOBS

Position name – SW Engineer

Experience: 1 to 3 years
Qualification: Bachelor’s engg degree in EE

Primary Responsibilities
 Software Development for Performance Audio Business

Secondary Responsibilities
 Customer support, Algorithm development for 67x, DA8x family class of processors. Audio systems expertise.

Technical abilities:
 C Programming, DSP Architecture, Embedded programming, Real Time OS

HPA HOT JOBS


Position Name - Lead Design Engineer

Experience: 4+ years
Qualification: BE/ME in Electronics

Work Description:
• Design lead - Architecture design, Circuit design, PG
• Silicon debug and char
• Application support

Requirements:
o Candidate should be an expert in one of more of the following:
o Amplifier
o Comparators
o Analog to Digital Converters
o Digital to Analog Converters
o Silicon debug and complete engineering from design to RTM.
o Strong in fundamentals in electrical Engineering.

Following expertise shall be an added advantage:
o Experience in resolving Yield/customer support issues.


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Position Name: Design Engineer

Experience: 2 to 5 years
Qualification: BE/ME in Electronics

Requirements:
o Candidate must have worked on design of one or more of the blocks such as:
o Amplifier
o Comparators
o Analog to Digital Converters
o Digital to Analog Converters
o Exposure to silicon
o Strong in fundamentals in electrical Engineering.

Following expertise shall be an added advantage:
o Silicon debug and complete engineering from design to RTM.


Position Name: Char/Test and Apps Engineer

Experience: 2 to 5 years
Qualification: BE/ME in Electronics

Requirements:
o Candidate should have worked on silicon characterization of :
o Analog to Digital Converters
o Digital to Analog Converters
o Phase Locked Loops,
o Silicon debug experience.
o Board design and flair for hardware
Exposure to bench test equipments and automation
o Strong in fundamentals in electrical Engineering.

Following expertise shall be an added advantage:
o Experience in resolving Yield/customer support issues.
o Product experience till RTM phase
o Candidate must have an engineering degree in electronics (BE or ME)
o Exposure to tester platform
o Design experience



Work Description:
• Characterization and silicon debug.
• Final test solution development

• Application support for the product
• Good understanding of the design

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Position Name: Test Engineer

Experience: 2 + years
Qualification: BE/ME in Electronics

Work Description :-Testing of Analog ICs. The specific tasks include design of Evaluation Boards that will house the device under the test. The challenge is in designing the hardware that performs better than the device so that the device performance can be measured accurately. The hardware design requires knowledge of basic Analog design skills including knowledge of RC circuits, OPAMP based circuit design, experience PCB design among others. The task also includes writing software that automates the testing. Knowledge of Automated Test Equipment (ATE) and experience in using them will be very useful

Position Name: Circuit Design Engineer

Experience: 2 + years
Qualification: BE/ME in Electronics

Work Description : Design of Mixed Signal Integrated Circuits. The work involves design of various analog blocks like Operational Amplifiers, Comparators, Oscillator, Analog to Digital Converter, etc. Responsible for designing, developing, modifying and evaluating electronic parts, components or integrated circuitry for electronic equipment and other hardware systems. Determine design approaches and parameters. Analyze equipment to establish operating data, conduct experimental tests and evaluates results.

The knowledge of various tools used in analog design like Spice/Spectre, Cadence design environment will be required.


ITS HOT JOBS

• UNIX L3 Admin:
o Experience: 4-5 yrs
o Primary Responsibilities:
 Manage and maintain a large base of computers running UNIX (Solaris/Linux).
o Secondary Responsibilities:
 Oncall support on weekly basis. (5:30 am – 5:30 pm)
o Skills:
 High comfort level with the Solaris 8/9 and Red Hat Linux 3.0 Enterprise operating system
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• UNIX Monitoring Engineer:
o Experience: 4-5 yrs (2 yrs working with BMC Patrol)
o Primary Responsibilities:
 Manage and maintains the monitoring solution for a large base of computers running UNIX/LINUX.
o Secondary Responsibilities:
 Provisions and provides support and training for standard monitoring solutions (BMC and Invoq products) in UNIX and Linux platforms.
 Oncall support (rotation by weekly)
o Skills:
 Detailed knowledge of all aspects of BMC Patrol and Patrol Express.
 Must have excellent troubleshooting skills in the areas of: UNIX (Solaris and Linux).


• Licensing Support Administrator:
o Experience: 5 -7 yrs
o Primary Responsibilities:
 Administration of License Servers worldwide & resolve all day-to-day EDA Licensing Problems within defined QoS/SLA framework.
o Secondary Responsibilities:
 Working closely with WPL & EDA Vendors to manage EDA licensing on WW Flames Servers (WPL & most EDA Vendors are USA Based).
o Skills:
 Knowledge of EDA Licensing Administration.
 In-Depth Knowledge of FLEXlm, FLEXNet, LM commands, RLM, Sam Suite & Various Licensing mechanism.

• Network Engineer:
o Experience: 7-8 yrs
o Primary Responsibilities:
 Responsible for the day-to-day operations of Network and Voice infrastructure services
o Secondary Responsibilities:
 Supporting and solving day-to-day network/voice incidents.
 Making and carrying out tactical decisions.
o Skills:
 Exposure to handling the voice/network infrastructure including Avaya and Cisco products.
 Knowledge in network (LAN/WAN) technologies /hardware platforms.
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• UNIX L2 Admin:
o Experience: 2-3 yrs
o Primary Responsibilities:
 Manage and maintain a large base of computers running UNIX (Solaris/Linux).
o Secondary Responsibilities:
 Oncall support on weekly basis. (5:30 am – 5:30 pm)
o Skills:
 High comfort level with the Solaris 8/9 and Red Hat Linux 3.0 Enterprise operating system.





SALES AND MARKETING HOT JOBS


Title – Analog Applications Engineer (HPA – Signal)
Enabling the customer in realizing development of analog designs using Data converters, Amplifiers, Interface etc.,
– by advocating
o the right topology and technology through creation / evaluation of schematics and block diagrams
- by advocating PCB layout guidelines
- by assisting in EMI/EMC recommendations

Profile:
- BE/ME with 3~5 years of design experience in analog and digital hardware design
- Strong fundamental Knowledge on analog signal processing
- Knowledge of Matlab and PSpice
- Working Knowledge of microcontrollers and DSPs will be added advantage

Location – Hyderabad, Delhi








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ALL-INDIA WALK-IN INTERVIEWS (DELHI, TRIVANDRUM, MUMBAI, PUNE, BANGALORE, CHENNAI) - FEBRUARY 23 & 24, 2008!!! (IFlex)

emp id: 23111

Name : koti siva Ramakrishna p



Education: B.E / B Tech/ MCA Selection: Technical Test (up to 4 years experience only ) + Interviews
Delhi Date: Feb 23, 2008 (Saturday) Time: 10am to 3pm

Role : Developer
Skillset : Cognos, Oracle
Work location : Bangalore
Exp : 3 thru 6 yrs

Venue:
Equinox Global Services Pvt. Ltd.
Block - A, First India Phase
Sushant Lok Phase - I
Gurgaon - 122002
Haryana.
Contact Number: 0124-5060365

Trivandrum Date: Feb 24, 2008 (Sunday) Time: 10am to 3pm

Role : Developer / Sr. Developer
Skillset : Java / JSP / Servlets / EJB
Work location : Bangalore
Exp : 2 thru 6 yrs

Role : Developer / Sr. Developer
Skillset : Oracle, PL/SQL
Work location : Bangalore
Exp : 3 thru 6 yrs
Venue:
The South Park
Kerala Hotels Pvt. Ltd
M G Road,
Trivandrum 695 034, Kerala.
Contact Number : 471-2333333
Bangalore Date: Feb 23, 2008 (Saturday) Time: 10am to 3pm

Role : Developer / Sr. Developer
Skillset : Java / JSP / Servlets / EJB
Work location : Bangalore
Exp : 2 thru 6 yrs

Role : Developer / Sr. Developer
Skillset : Oracle, PL/SQL
Work location : Bangalore
Exp : 3 thru 6 yrs

Role : Developer
Skillset : Cognos, Oracle.
Work location : Bangalore
Exp : 3 thru 6 yrs

Venue:
i-flex solutions limited
Lower Ground floor, B Tower
Diamond District
Airport Road
Bangalore – 560 008, India
Contact Number: 080-66219000 / 3983 9000


Role : Sr. Developer / Tech Lead / Project Lead
Skillset :Oracle PL/SQL with experience in web
development using Java\J2EE, EJB,
JDBC, XML. Experience in managing
a team of 3- 5 is mandatory.
Experience in banking projects is
mandatory for candidates with 8+ yrs
of experience
Work location : Bangalore
Exp : 3 thru 10 yrs

Role : Developer
Skillset : C, C++, VC++ with PL/SQL. Knowledge of XML, XSL programming. Should be willing to work in Night Shifts.
Work location : Bangalore
Exp : 2 thru 4 yrs
Venue:
i-flex solutions limited
i-flex park, Embassy Business Park,
C V Raman Nagar,
Bangalore - 560 093

Contact Number: 080 6659 3000
Mumbai Date: Feb 23, 2008 (Saturday) Time: 10am to 3pm

Role : Developer / Sr. Developer
Skillset : VB .Net, C#, .Net Application
Work location : Mumbai
Exp : 3 thru 6 yrs

Role : Developer / Sr. Developer
Skillset : Java, J2EE
Work location : Mumbai
Exp : 2 thru 6 yrs

Role : Test Engineers
Skillset : Automation Testing – QTP, Load
Runner, Rational Robot. Manual Testers
with finance domain.
Work location : Mumbai
Exp : 3 thru 6 yrs

Role : Developer / Sr. Developer
Skillset : Oracle, PL/SQL
Work location : Mumbai
Exp : 3 thru 6 yrs
Venue:
i-flex Park
Nirlon Complex, Near Hub mall
Goregaon East
Mumbai - 400063

Contact Number: 022 6718 8000




Role : Developer / Sr. Developer / Tech Lead
Skillset : Java / JSP / Servlets / EJB.
Work location : Mumbai
Exp : 3 thru 8 yrs

Role : Developer / Sr. Developer / Tech Lead
Skillset : Oracle, PL/SQL
Work location : Mumbai
Exp : 3 thru 8 yrs
Venue:
i-flex Annexe
Nirlon Complex, Near Hub mall
Goregaon East
Mumbai - 400063

Contact Number: 022-6718-8000

Mumbai Date: Feb 24, 2008 (Sunday) Time: 10am to 3pm

Role : Developer / Sr. Developer
Skillset : Java, J2EE
Work location : Mumbai
Exp : 2 thru 6 yrs

Venue:
i-flex Park
Nirlon Complex, Near Hub mall
Goregaon East
Mumbai - 400063

Contact Number: 022 6718 8000

Pune Date: Feb 23, 2008 (Saturday) Time: 10am to 3pm

Role : Developer / Sr. Developer / Tech Lead
Skillset : Java / JSP / Servlets / EJB with any RDBMS
Work location : Pune
Exp : 2 thru 6 yrs

Role : Developer / Sr. Developer / Tech Lead
Skillset : Oracle, PL/SQL
Work location : Pune
Exp : 2 thru 8 yrs

Venue:
i-flex Heights,
Lohia Jain IT Park,
Bhusari Colony,
Paud Road,
Kothrud,
Pune – 411029

Contact Number: 020-6670 7000

Chennai Date: Feb 23, 2008 (Saturday) Time: 10am to 3pm

Role : Sr. Developer
Skillset : Oracle, PL/SQL.
Work location : Bangalore
Exp : 4 thru 6 yrs

Role : Developer / Sr. Developer
Skillset : Java / JSP / Servlets / EJB.
Work location : Chennai / Bangalore
Exp : 2 thru 6 yrs

Venue:
i-flex solutions limited
143/1, Uttamar Gandhi Salai
Nungambakkam,
Chennai - 600 034

Contact Number: 044- 6678 4000